Minimization of Leakage Current in VLSI Design

To meet the ever-increasing demand of high performance systems, more and more functions are integrated into single chip by scaling down the size of device. Leakage current is becoming an increasingly important fraction of total power dissipation of integrated circuits. As technology scales leakage current grows exponentially and become and increasingly large component of total power dissipation. An important area of research is developing the circuit techniques to reduce the subthreshold leakage current in both active and standby mode to minimize the total power consumption. The power dissipation due to subthreshold leakage current becomes comparable to switching or dynamic power component and is a serious concern for circuit designing in deep submicron region. This paper describes the need to consider gate leakage current while determining the sleep state pattern is explained. Circuit reorganization and sleep state assignment techniques demonstrated for gate and subthreshold minimization of static and dynamic circuits. The MTCMOS technology for the minimization of gate and subthreshold leakage current is also explained for the low power circuits.